1. Field of the Invention
The present invention relates to a matched filter used in a code division multiple access (CDMA) receiver for determining the correlation between input data and scrambling codes.
2. Description of the Related Art
Generally, a CDMA transmission/reception system is adapted to multiple access, using scrambling/descrambling operation, a plurality of scrambling codes and carrier waves of the same frequency. This will be explained later in detail.
With the CDMA transmission/reception system, however, a receiver cannot correctly carry out a descrambling operation if it misses the right timing of scrambling operation carried out by a base station.
Additionally, since each base station has a plurality of scrambling codes it uses, the receiver cannot know in advance the scrambling code being used by the base station to be accessed by the receiver. However, if the receiver cannot get any information from the base station, the receiver cannot access the base station unless it can specifically know the scrambling code that the base station uses.
A perch function using a matched filter is used to solve the above-mentioned problem. This also will be explained later in detail.
A prior art matched filter is accompanied by the following problems. The operation of obtaining the scrambling timing and that of identifying a scrambling code being used by the base station are carried out independently at different timings, so that a discrepancy in the correlating timing and, in the worst case, a total incapability of signal reception can occur. Also, half of the power used for receiving the codes is consumed for nothing.
It is an object of the present invention to provide a matched filter that can carry out an operation of obtaining the timing of a base station by using a known scrambling code contained in a long code mask symbol and an operation of determining if a selected scrambling code agrees with a scrambling code contained in the logic symbol.
According to the present invention, in a matched filter, a plurality of data holding circuits adapted to sequentially hold a plurality of straight binary data and a plurality of correlators are provided. Each of the correlators receiving one bit of a known code such as a known scrambling code and one bit of a selected code such as a scrambling code selected by a base station as a 2-bit code, outputs the straight binary data as it is when the 2-bit code is xe2x80x9c00xe2x80x9d, outputs the straight binary data after logically inverting the straight binary data when the 2-bit code is xe2x80x9c11xe2x80x9d, and outputs exclusive OR values between the straight binary data except for its most significant bit and the most significant bit while outputting xe2x80x9c1xe2x80x9dfor the most significant bit when the 2-bit code is one of xe2x80x9c01xe2x80x9d and xe2x80x9c10xe2x80x9d. Also, an adder adds output signals of the correlators and outputs an addition result as a correlation value.